1. MSEE or Ph.D. in Electrical Engineering.
2. Require 8+ years of analog IC design experiences.

1. Require supervisory experience.
2. Require MSEE and 5+ years of analog IC design experiences.

1. Familiar with Verilog / RTL / STA / Simulation ... other verification flow
2. Proficient in programming skill and UNIX shell
3. MBIST / Scan diagnosis experience and ATE test debug experience
4. System level MBIST planning / Knowledge of boundary scan
5. Compression / Share code / Ultra flow implement experience
6. EDA development for logic design flow and DFT flow
7. Experience in IC design file, familiar DFT of MBIST/ SCAN skills
8. 5 years above of working experience

5 years above of working experience

1. Over 3-year digital design experiences
2. Familiar with DDR/LPDDR/HBM/SerDes or DSP is plus
3. Familar with digital IC front-end design flow such as Verilog RTL design, Synopsys Design
4. Compiler, LEC, Spygalss, PrimeTime STA
5. 3 years above of working experience

1. Fundamentals and roles in all processing steps of forming 3D memory devices, peripheral devices and their IC circuit
2. Strong understanding of surface and analytical characterization techniques such as SEM, TEM, CDSEM, XPS, AFM, XRD, AES, EBSD, SIMS etc.
3. Deep understanding of various dielectric /electrical evaluation methods and techniques such as leakage, breakdown, resistance, & on current
4. Experience and/or in-depth knowledge of process ownership and development
5. Interact and collaborate with integration engineers to develop robust unit process and related module as well as transfer the process to production fab
6. Excellent verbal and written communication skill
7. M.S. or PhD in Chemical Engineering, Materials Science, Chemistry or related discipline is required
8. Must have technical expertise within semiconductor processing engineering preferably in 3D Memory process development for leading edge technology
9. 10 years of experience in semiconductor process development is desired

1. Experience with MCU/MPU system architecture and performance requirement
2. Experience in Tier-1 MCU companies is preferred

1. Experience with MCU/MPU Market and Product
2. 10 years MCU experience with at least 5 years worked on the MCU marketing

1. MS with 5+ years of experience in Physical Design.
2. Familiar with Unix/Linux environment and scripts
3. Familiar with ASIC design flow
4. Familiar with Physical Design EDA tools.
5. Good communication and team working skills
6. Experience in handling large scale SoC chip implementation is a plus
7. 5 years of working experience

1. MS or PhD degree in EE or Communication
2. Experience in communication system PHY algorithm development
3. In depth knowledge on theories and implementations of digital signal processing, channel coding, and communication system
4. Familiar with commercial wired or wireless communication specifications
5. Familiar with Matlab and C/C++
6. Experience in RF/AFE system design, impairment modeling, calibration, mixed-mode system architecture is a plus.
7. 5 years of working experience